Semiconductor device and method for fabricating the same

ABSTRACT

Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention claims priority of Korean patent applicationnumber 10-2008-0083998, filed on Aug. 27, 2008, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for fabricating a gate of asemiconductor device, and more particularly, to a method for forming anisolation layer for a trench.

2. Description of Related Art

As the integration extent of a semiconductor device increases, manyresearches have been made to develop a technology for reducing anisolation region. Shallow Trench Isolation (STI) was introduced as anisolation technology for the next generation devices having highintegration through flatness of an isolation region and precise designrule.

FIG. 1A is a plane view illustrating a typical gate of a metal oxidesemiconductor (MOS) transistor according to the related art, and FIG. 1Bis a cross-sectional view illustrating the gate of FIG. 1 taken alongthe line I-I′. FIGS. 2A to 2H are cross-sectional views illustrating thegate of FIG. 1A taken along the line I-I′ for describing a STI process.

As shown in FIG. 2A, a pad oxide layer 102 and a pad nitride layer 104are formed on a substrate 100.

As shown in FIG. 2B, an etch mask 106 for forming a trench is formed onthe pad nitride layer 104.

As shown in FIG. 2C, trenches 108 are formed in the substrate 100 byperforming an etch process using the etch mask 106. In the etch process,the pad nitride layer 104, the pad oxide layer 102, and the substrate100 are partially etched. As a result, a pad nitride pattern 104A, a padoxide layer pattern 102A, and a substrate 100A internally having thetrenches 108 are formed.

As shown in FIG. 2D, the etch mask 106 (see FIG. 2C) is removed.

Then, a sidewall passivation layer 110 is formed on an inner side of thetrenches 108.

As shown in FIG. 2E, an insulation layer 112 is deposited until fillingup the trenches 108.

As shown in FIG. 2F, a first isolation layer pattern 112A is formed inthe trenches 108 by removing the pad nitride layer pattern 104A (seeFIG. 2E) after polishing the insulation layer 112 (see FIG. 2E).

As shown in FIG. 2G, the pad oxide layer pattern 102A (see FIG. 2F) isremoved by etching the pad oxide layer pattern 102A. In this process,portions of the first isolation layer pattern 112A and the sidewallpassivation pattern 110 are also etched to thereby form a secondisolation layer pattern 112B and a sidewall passivation pattern 110A

Then, a gate insulation layer 114 and a gate conductive layer 116 areformed on an active region 101 of the substrate 100A as shown in FIG. 1Band FIG. 2H. Here, the gate insulation layer 114 is formed by oxidizingthe active region 101 through an oxidation process performed in anoxygen (O₂) atmosphere.

However, the STI process of the semiconductor device according to therelated art has following problems.

In FIG. 2D, the sidewall passivation layer 110 is formed by oxidizingthe inner sidewall of the trench through an oxidizing process. Sinceimpurities in the substrate 100A are absorbed at the sidewallpassivation layer 110, the impurity concentration of an upper cornerportion 120 (see FIG. 2H) of the trench 108 varies. The impurityconcentration in the substrate 100A effects the growth of the gateinsulation layer 114.

Therefore, the growth of the gate insulation layer becomes thinner thana target thickness at the upper corner portion of the trench 108 asshown in FIG. 3 when the gate insulation layer 114 is grown in FIG. 2H.Accordingly, the gate insulation layer cannot be uniformly grown, abreakdown voltage is reduced and gate oxide integrity (GOI) isdeteriorated as shown in FIG. 4.

Furthermore, a parasitic transistor having a threshold voltage lowerthan an original channel is formed due to the impurity concentrationvariation of the upper corner portion 120 of the trench 108. Therefore,a leakage current increases when an OFF operation of a transistor isperformed. Such a leakage current deteriorates the performance of atransistor that functions as a switching element and degrades thresholdvoltage mismatching. As shown FIG. 5, a product thereof may perform pooroperation because it shows an I-V curve characteristic that cannot beexpressed as a SPICE model.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to providing asemiconductor device and a fabricating method thereof for forming a gateinsulation layer with a uniform thickness by preventing a thin gateinsulation layer from forming at an upper corner portion of a trench.

In accordance with an aspect of the present invention, there is provideda semiconductor device including a substrate having a trench thatdefines an active region, an isolation layer that buries the trench, apro-oxidant region formed at an upper corner portion of the trench toenhance oxidation at the upper corner portion of the trench when a gateinsulation layer is grown on the active region, and a gate conductivelayer formed on the gate insulation layer.

In accordance with another aspect of the present invention, there isprovided a method for fabricating a semiconductor device includingdefining an active region by forming a trench in a substrate, forming anisolation layer in the trench, forming a pro-oxidant region at an uppercorner portion of the trench, forming a gate insulation layer byoxidizing the active region, and forming a gate conductive layer on thegate insulation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a typical semiconductor device.

FIGS. 2A to 2H are cross-sectional views of FIG. 1 taken along the lineI-I′ to describe a method for fabricating a semiconductor deviceaccording to the related art.

FIG. 3 is a cross-sectional view of the typical semiconductor device.

FIG. 4 is a graph showing gate oxide integrity (GOI) analysis result ofa semiconductor device according to the related art.

FIG. 5 is a graph showing I-V character of a semiconductor deviceaccording to the related art.

FIG. 6 is a plane view of a semiconductor device in accordance with thefirst embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views of FIG. 6 taken along thelines I-I′ and II-II′.

FIGS. 8A to 8E are cross-sectional views describing a method forfabricating a semiconductor device in accordance with the firstembodiment of the present invention.

FIG. 9 is a plane view of a semiconductor device in accordance with asecond embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views of FIG. 9 taken along thelines I-I′ and II-II′.

FIG. 11 is a plane view of a semiconductor device in accordance with athird embodiment of the present invention.

FIGS. 12A and 12B are cross-sectional views of FIG. 10 taken along thelines I-I′ and II-II′.

FIG. 13 is a cross-sectional view of a semiconductor device employingembodiments of the present invention.

FIG. 14 is a graph showing GOI analysis result of a semiconductor deviceemploying embodiments of the present invention.

FIG. 15 is a graph showing I-V character of a semiconductor deviceemploying embodiments of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Other objects and advantages of the present invention can be understoodby the following description, and become apparent with reference to theembodiments of the present invention. In the drawings, the thickness oflayers and regions and gap are exaggerated for clarity and convenience.It will be understood that when a layer is referred to as being “on”another layer, it can be directly on the other layer or interveninglayer may also be present. Also, a third layer may be interposedtherebetween. Through the specification, like reference numeralsdesignate like elements. If a reference numeral includes alphabets, itdenotes the same layer is modified by etching or polishing process.

FIG. 6 is a plane view of a semiconductor device in accordance with afirst embodiment of the present invention, and FIGS. 7A and 7B arecross-sectional views illustrating the semiconductor device of FIG. 6taken along the lines I-I′ and II-II′.

Referring to FIGS. 6 to 7B, the semiconductor device according to thefirst embodiment includes a substrate 200A having a trench 203 and apro-oxidant region 207 formed at an upper corner portion of the trench203.

The pro-oxidant region 207 is formed to enhance oxidation (growth rate)at a predetermined portion, particularly, an upper corner portion of thetrench in an oxidation process for forming a gate insulation layer 208.The pro-oxidant region 207 may be formed by implanting impurity ionshaving a conductive type identical to or different from that of thesubstrate 200A. Also, the pro-oxidant region 207 may be formed atconcentration higher than impurity concentration of the substrate 200Afor further enhancing the oxidation if the pro-oxidation region 207 isformed by implanting impurity ions having the same conductive type ofthe substrate 200A. For example, the pro-oxidant region 207 is formed atconcentration higher than concentration of a well if the substrate 200Aincludes the well (not shown). Furthermore, the pro-oxidant region 207is formed at a shallower depth from the top surface of the substrate200A than the trench 208.

The semiconductor device according to the first embodiment furtherincludes an isolation layer 205B buried in the trench 203, a gateinsulation layer 208 formed by oxidizing the substrate 200A, and a gateconductive layer 209 formed on the gate insulation layer 208. The gateinsulation layer 208 is formed on an active region defined by the trench203. The semiconductor device according to the first embodiment furtherincludes a source and drain region 210 formed on active regions exposedat both sides of the gate conductive layer 209, and a junction region211.

The active region has a box type. The gate conductive layer 209 isformed in a direction that crosses the active region. The gateconductive layer 209 may be formed in a short-axis direction of theactive region.

The pro-oxidant region 207 is formed to surround an outline of theactive region. Here, the pro-oxidant region 207 may be formed in theisolation layer 205B as well as the active region. In this case, thepro-oxidant region 207 is formed in a sidewall passivation layer 204Aformed between the active region and the isolation layer 205B.

Also, the pro-oxidant region 207 may be formed at a region where thegate conductive layer 209 overlaps with the active region. Thepro-oxidant region 207 may be formed in the isolation layer 205B as wellas the active region. In this case, the pro-oxidant region 207 is formedin the sidewall passivation layer 204A formed between the active regionand the isolation layer 205B. In addition, the pro-oxidant region 207may be selectively formed only in the active region except the isolationlayer 205B.

Hereinafter, a method for fabricating a semiconductor device accordingto the first embodiment of the present invention will be described.

FIGS. 8A to 8E are cross-sectional views describing a method forfabricating a semiconductor device in accordance with the firstembodiment of the present invention.

As shown in FIG. 8A, a substrate 200 is prepared. The substrate 200 is asemiconductor substrate made of one selected from the group consistingof Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Also, thesubstrate 200 has a p-type or an n-type.

Then, an ion implantation process for controlling a threshold voltage ina channel region is performed after forming a well in the substrate 200.

A pad oxide layer 201 as a buffer layer and a pad nitride layer 202 as ahard mask are formed on the substrate 200. The pad oxide layer 201 isformed to prevent the surface of the substrate 200 from being damagedwhen depositing the pad nitride layer 202.

The pad oxide layer 201 is formed through an oxidation process. Forexample, a silicon oxide layer is formed. The pad nitride layer 202 isformed through a low pressure chemical vapor deposition (LPCVD) processfor minimizing stress applied to the substrate 200 when depositing thepad nitride layer. For example, the pad nitride layer 202 is made of asilicon nitride layer. Or, the pad nitride layer may be a multilayerstacked of a nitride layer (silicon nitride layer), an oxide layer(silicon oxidation layer), and an oxynitride layer (silicon oxynitridelayer SiON).

As shown in FIG. 8B, the trench 203 is formed through etching.

The trench 203 is formed as follows. A pad nitride layer pattern 202A isformed using an etch mask such as a photoresist pattern for forming atrench. Then, a pad oxide layer pattern 201A is formed using the padnitride pattern 202A. A plurality of trenches 203 are formed in thesubstrate 203 by etching a portion of the substrate 200A. Here, a dryetch process is performed for a vertical profile of an inner surface ofthe trench 203, that is, an etch surface. For example, the dry etchprocess is performed using a plasma etch equipment.

Also, a hydrogen bromide (HBr) gas or a chlorine (Cl₂) gas is used as anetch gas. Or, gas mixture of HBr/Cl₂/O₂ may be used as the etch gas.

As shown in FIG. 8C, a sidewall passivation layer 204 is formed on aninner side of the trench 203. The sidewall passivation layer 204 isformed by rounding the etch surface, that is, the inner side of thetrench 203 and performing an oxidation process for preventing electricfield from concentrating at a corner. For example, a silicon oxide layeris formed through a dry etch process or a wet etch process.

Then, an isolation layer 205 is formed until the trench 203 is buried.Here, the isolation layer 205 may be formed as a un-doped silicate glass(USG) layer using high density plasma-chemical vapor deposition(HDP-CVD) providing a superior filling-up character even in a highaspect ratio. Or, the isolation layer 205 may be formed in a stackingstructure of the HDP layer and a spin on dielectric (SOD) layer. Here, apolisilazane (PSZ) layer may be used as the SOD layer. In addition,material that can be formed through a spin coating scheme may be used.Also, the isolation layer 205 may be formed of BoronPhosphoSilicateGlass (BPSG), PhosphoSilicate Glass (PSG), Tetra Ethyle Ortho Silicate(TEOS), or a stack layer thereof.

As shown in FIG. 8D, the pad nitride layer pattern 202A (see FIG. 8C) isselectively removed. The process of removing the pad nitride pattern202A uses a phosphoric acid solution (H₃PO₄).

Then, a cleaning process may be performed. The cleaning process uses aBuffered Oxide Etchant (BOE) solution or a Diluted HF (DHF) solution forremoving foreign substance such as particles.

Meanwhile, the isolation layer 205A may be recessed at the height of thepad oxide layer 201A because the isolation layer 205A is etched at apredetermined thickness through the process of removing the pad nitridelayer pattern 202A and the cleaning process.

Then, a pro-oxidant region 207 is formed at an upper corner portion ofthe trench 203. The pro-oxidant region 207 is formed by implantingimpurity ions having a conductive type identical to or different fromthe substrate 200A. Also, the pro-oxidant region 207 is formed atconcentration higher than the impurity concentration of the substrate200A. Also, the pro-oxidant region 207 is formed at a shallower depthfrom the top surface of the substrate 200A than the trench 203. Here,the pro-oxidant region 207 may be formed through ion implantation ordiffusion. For example, the ion implantation process is performed usingboron (B), which is a group III element, and phosphorus (P) and arsenic(As), which are group VI elements. The diffusion process diffuses boron(B) using an impurity gas B₂H₆ or diffuses arsenic (As) using animpurity gas PH₄. Here, an argon gas (Ar) and a nitrogen gas (N₂) areused as a transport gas.

As shown in FIG. 8E, the pad oxide layer 201A (see FIG. 8D) is removed.In this step, the isolation layer 205B may be recessed at apredetermined depth. Therefore, the isolation layer 205B may be lowerthan the top surface of the substrate 200A.

Then, a gate insulation layer 208 is formed on the substrate 200A. Here,the gate insulation layer 208 is formed by oxidizing the substrate 200A.For example, the gate insulation layer 208 is formed of a silicon oxidelayer. After forming the silicon oxide layer, a nitride layer may befurther formed on an interface between the silicon oxide layer and thesubstrate 200A by performing a thermal process using a nitrogen gas (N₂)after forming the silicon oxide layer. A dry oxidation process, a wetoxidation process, or a radical ion oxidation process may be performedfor oxidizing the substrate 200A. It is preferable to perform the dryoxidation process and the wet oxidation process instead of the radicalion oxidation process.

Then, a gate conductive layer 209 is formed on the gate insulation layer208. The gate conductive layer 209 is made of one selected from thegroup consisting of a polysilicon layer, a transition metal, and rareearth element metals. The gate conductive layer 209 may made of apolysilicon layer that has a superior interface character with the gateinsulation layer 208 and can be etched easier than metal. For example,the polysilicon layer is formed through the LPCVD method. A SiH₄ gas isused as a source gas, and a PH₃ gas is used as a doping gas. Also, iron(Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), white gold(Pt), molybdenum (Mo), or titanium (Ti) is used as the transition metal.

Also, erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), lanthanum(La), cerium (Ce), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium(Tm), and lutetium (Lu), are used as the rare earth element.

FIG. 9 is a plane view of a semiconductor device in accordance with asecond embodiment of the present invention, and FIGS. 10A and 10B arecross-sectional views of FIG. 9 taken along the lines I-I′ and II-II′.

Referring to FIGS. 9 to 10B, the semiconductor device according to thesecond embodiment basically has a structure identical to the firstembodiment. Unlike the first embodiment that the pro-oxidant region 207is formed to surround the outline of the active region, a pro-oxidantregion 304 of the second embodiment is locally formed in a bar type at aregion where a gate conductive layer 306 overlaps with an active region.Here, the pro-oxidant region 304 is formed in the active region and theisolation layer 303.

Since the other constituent elements of the second embodiment areidentical to those of the first embodiment, the detail descriptionsthereof are omitted. In FIGS. 9 and 10, a reference numeral 301 denotesa trench, a reference numeral 302 denotes a sidewall passivation layer,a reference numeral 303 is an isolation layer, a reference numeral 305is a gate insulation layer, a reference numeral 307 is a source anddrain region, and a reference numeral 308 is a junction region.

FIG. 11 is a plane view of a semiconductor device in accordance with athird embodiment of the present invention, and FIGS. 12A and 10B arecross-sectional views of FIG. 11 taken along the lines I-I′ and II-II′.

Referring to FIGS. 11 to 12B, a pro-oxidant region 404 of thesemiconductor device according to the third embodiment is locally formedin a bar type at a region where a gate conductive layer 406 overlapswith an active region like the pro-oxidant region 404 of the secondembodiment. The pro-oxidant region 404 is formed only in an activeregion.

Since other constituent elements are identical to those of the firstembodiment, the detail descriptions thereof are omitted. In FIGS. 10 and11, a reference numeral 401 denotes a trench, a reference numeral 402 isa sidewall passivation layer, a reference numeral 403 is an isolationlayer, a reference numeral 405 is a gate insulation layer, a referencenumeral 407 is a source and drain region, and a reference numeral 408 isa junction region.

Hereinafter, effects of the first to third embodiments of the presentinvention will be described.

FIG. 13 is a cross-sectional view of a semiconductor device employingembodiments of the present invention. FIG. 14 is a graph showing GOIanalysis result of a semiconductor device employing embodiments of thepresent invention, and FIG. 15 is a graph showing I-V character of asemiconductor device employing embodiments of the present invention.

FIG. 13 clearly shows the gate insulation layer formed at the uppercorner portion of the trench at a uniform thickness. That is, thepro-oxidant region enables the gate insulation layer to be stably grownat the upper corner portion of the trench.

The GOI analysis result graph of FIG. 14 clearly shows that the GOIcharacteristic is significantly improved when the embodiments of thepresent invention are applied (After) compared to GOI characteristic ofthe related art. That is, the breakdown voltage is improvedsignificantly when the embodiments of the present invention are applied,compared to the related art. As shown in FIG. 15, an ideal V-I curve canbe obtained if the embodiments of the present invention are applied,compared to the related art (see FIG. 5).

Embodiments of the present invention relate to a semiconductor deviceand a fabricating method thereof. In the present invention, apro-oxidant region is formed at an upper corner region of a trench inorder to enhance the growth of a gate insulation layer at the uppercorner portion of the trench for forming the gate insulation layer at auniform thickness. Therefore, GOI character and I-V character can beimproved as well as a breakdown voltage.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A semiconductor device, comprising: a substrate having a trench thatdefines an active region; an isolation layer that buries the trench; apro-oxidant region formed at an upper corner portion of the trench toenhance oxidation at the upper corner portion of the trench when a gateinsulation layer is grown on the active region; and a gate conductivelayer formed on the gate insulation layer.
 2. The semiconductor deviceof claim 1, wherein the pro-oxidant region is formed by implantingimpurity ions having a conductive type identical to the substrate. 3.The semiconductor device of claim 2, wherein the pro-oxidant region isformed at concentration higher than the substrate.
 4. The semiconductordevice of claim 3, wherein the pro-oxidant region is formed byimplanting one selected from the group consisting of boron ion (B),phosphorus ion (P), and arsenic ion (As).
 5. The semiconductor device ofclaim 1, wherein the pro-oxidant region is formed by implantingimpurities having a conductive type different from the substrate.
 6. Thesemiconductor device of claim 1, wherein the active region has a boxtype.
 7. The semiconductor device of claim 6, wherein the gateconductive layer is formed in a direction crossing the active region. 8.The semiconductor device of claim 7, wherein the pro-oxidant region isformed to surround the active regions.
 9. The semiconductor device ofclaim 8, wherein the pro-oxidant region is formed in the active regionand the isolation layer.
 10. The semiconductor device of claim 7,wherein the pro-oxidant region is formed in a bar type at a region wherethe gate conductive layer overlaps with the active region.
 11. Thesemiconductor device of claim 10, wherein the pro-oxidant region isformed in the active region and the isolation layer.
 12. Thesemiconductor device of claim 10, wherein the pro-oxidant region isformed in the active region, not in the isolation layer.
 13. Thesemiconductor device of claim 1, further comprising a sidewallpassivation layer formed by oxidizing an inner side of the trenchbetween the trench and the isolation layer.
 14. The semiconductor deviceof claim 13, wherein the pro-oxidant region is formed in the sidewallpassivation layer between the active region and the isolation layer. 15.The semiconductor device of claim 15, wherein the isolation layer isformed to be lower than a top surface of the substrate.
 16. A method forfabricating a semiconductor device, comprising: defining an activeregion by forming a trench in a substrate; forming an isolation layer inthe trench; forming a pro-oxidant region at an upper corner portion ofthe trench; forming a gate insulation layer by oxidizing the activeregion; and forming a gate conductive layer on the gate insulationlayer.
 17. The method of claim 16, wherein the pro-oxidant region isformed by implanting impurities having a conductive type identical tothe substrate.
 18. The method of claim 17, wherein the pro-oxidantregion is formed at concentration higher than the substrate.
 19. Themethod of claim 18, wherein the pro-oxidant region is formed byimplanting one selected from the group consisting of boron ion (B),phosphorus ion (P), and arsenic ion (As).
 20. The method of claim 16,wherein the pro-oxidant region is formed by implanting impurities havinga conductive type different from the substrate.
 21. The method of claim16, wherein the active region is formed in a box type.
 22. The method ofclaim 16, wherein the gate conductive layer is formed in a directioncrossing the active region.
 23. The method of claim 22, wherein thepro-oxidant region is formed to surround the active region.
 24. Themethod of claim 23, wherein the pro-oxidant region is formed in theactive region and the isolation layer.
 25. The method of claim 16,wherein the pro-oxidant region is formed in a bar type at a region wherethe gate conductive layer overlaps with the active region.
 26. Themethod of claim 25, wherein the pro-oxidant region is formed in theactive region and the isolation layer.
 27. The method of claim 25,wherein the pro-oxidant region is formed in the active region, not inthe isolation layer.
 28. The method of claim 16, further comprisingforming a sidewall passivation layer by oxidizing an inner side of thetrench after said defining an active region.
 29. The method of claim 28,wherein the pro-oxidant region is formed in the sidewall passivationlayer between the active region and the isolation layer.
 30. The methodof claim 16, wherein the isolation layer is formed to be lower than atop surface of the substrate.